Practice portal › Semiconductor Electronics › Digital Electronics and Logic Gates
Asked in NEET 2022 · Gate combinations and truth tables
| A | B | C |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
| A | B | C |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| A | B | C |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
| A | B | C |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| A | B | C |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Idea: write both NAND outputs in Boolean form and multiply them, then simplify.
The upper gate has A and B on it, so it gives A· B.
The lower gate has A and B on it, so it gives A· B.
The final AND gives C=A· B·A· B=(A+B)(A+B).
Expanding, C=AA+AB+BA+BB=B, since AA=0 and the rest all carry B.
So C=B: 00→1, 01→0, 10→1, 11→0, which is the third table.
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